As the performance and complexity of integrated circuits (IC) has increased over the years, the number of input/output (I/O) pin count has also increased significantly. High density devices with high output pin count may have a large number of output pins that may require output short circuit current (IOS) testing. It is a common practice to perform output IOS testing in order to verify the integrity of a device output protective circuit in the event of short on the output pins. IOS test simulate the worst-case loading conditions on the output pin of a device. The test guarantees that whenever output current exceeds the trip point for the IOS detection in the event of a short, the current limiting block would kick in to prevent the device from exceeding its absolute maximum current carrying capability and protect the device from any damage. The IOS test is performed using a test device commonly referred to as ATE (automatic test equipment), which either sources or sinks current to the output pins being tested while simulating a short circuit from the pin to ground by forcing the output pin to 0V. In the absence of a fault condition, the ATE should detect a current flow from the output pin not exceeding the allowable limited current from the device protective circuit. If, however, there is a defect in the current protective circuit and the current limiting failed, a huge amount of current may flow out from the device and thus register a substantial increase in current measurement at the output pin.
IOS test may be performed serially by measuring current on each output pin by pin or it can be performed simultaneously for all the output pins depend on the tester resources capability and availability. Due to the tester current measuring resources capability and availability limitation in ATE environment, IOS testing is commonly performed serially pin by pin, which takes a significant amount of test time.
A chip scale package (CSP) is a type of integrated circuit chip carrier. In order to qualify as chip scale, the package typically has an area no greater than 1.2 times that of the die and it is a single-die, direct surface mountable package. Another criterion that is often applied to qualify these packages as CSPs is their ball pitch should be no more than 1 mm.
The die may be mounted on an interposer upon which pads or balls are formed, like with flip chip ball grid array (BGA) packaging, or the pads may be etched or printed directly onto the silicon wafer, resulting in a package very close to the size of the silicon die. Such a package is called a wafer-level chip-scale package (WL-CSP) or a wafer-level package (WLP).
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.